Staff Design Verification Engineer, HBM Architecture
Core
Design and deliver scalable verification solutions for next-generation High Bandwidth Memory (HBM) DRAM products used in AI and ML applications, focusing on 2.5D & 3D package integration and low power per bit.
Role type
Staff Design Verification Architect (HBM Architecture)
Builds
Custom digital and RTL2GDS flow verification solutions for HBM stacks
Domain
Semiconductor / Memory / AI & ML Infrastructure
Deliverable
production ML models | product features
Required skills
Testbench architecture, custom and SoC verification methodologies, 2.5D & 3D package integration, digital (Verilog) verification, analog (FastSpice) verification, mixed-signal verification (co-sims or real number modeling), root cause analysis, feasibility analysis
Preferred skills
JEDEC specifications (HBM), building verification flows from scratch, GenAI applications in verification, patenting or publishing in verification solutions
Technologies
Verilog, FastSpice, TSV, RTL2GDS, SoC
Responsibilities
Develop turnkey verification solutions for future designs based on customer look-ahead information; Drive co-verification through direct customer interactions; Build verification methodology improvements and GenAI applications; Debug and identify root causes for pre-silicon and post-silicon issues
Seniority
Staff, hands-on IC with mentorship