Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering
Core
Develop and enable deployment of post-fab wafer finishing processes for high-performance memory products (HBM) to meet performance, cost, and reliability requirements.
Role type
Principal/Staff/Senior Engineer, Semiconductor Process Development (Wafer Level Packaging)
Builds
High bandwidth memory (HBM) packages and advanced packaging solutions for AI and data center applications
Domain
Semiconductor manufacturing, Advanced Packaging, Wafer Level Technology
Required skills
Semiconductor process development, Wafer bonding, Plating, Warpage control, Chemistry, Chemical kinetics, Thermodynamics, Mass transport, Films and interface engineering, SIMS, XPS, EDX, SEM/TEM, Python, R, SQL, Visual Basic, E3, FDC, RMS, SPC, DOE, Data analytics (via careerplan.io/jobs/38193998-principalstaffsenior-engineer-aptd-cem-advanced-packaging-wafer-level-technology-engineeri)
Preferred skills
Global collaboration, Cross-functional leadership, AI tool integration
Technologies
Photolithography, Dry etch, CMP, Wet process, Deposition, Plating, Wafer bonding, Wafer thinning, E3, FDC, RMS
Responsibilities
Establish and improve process management projects for next-node scaling; Identify disruptive processes and viable paths forward; Design and implement advanced process monitoring and control methodologies; Evaluate and promote new equipment and materials; Ensure defense coverage through process, measurement, inspection, and testing; Integrate and troubleshoot processes to drive yield and quality improvement; Provide Process Of Record (POR) and Model Of Record (MOR) documentation for product transfer.
Seniority
Principal/Staff/Senior, hands-on IC with strategic oversight