Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering
Core
Developing and enabling deployment of post-fab wafer finishing processes in semiconductor manufacturing to meet performance, cost, and reliability requirements for high-performance memory products.
Role type
Principal/Staff/Senior Engineer, Advanced Packaging Wafer Level Technology
Builds
High bandwidth memory (HBM) and advanced packaging solutions for AI and supercomputing
Domain
Semiconductor manufacturing / Advanced Packaging / Wafer Level Technology
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Wafer thinning, backside metal interconnect, process development, statistical analysis, process modeling, data analytics, root cause analysis, yield optimization, process flow management, equipment evaluation, material evaluation
Preferred skills
Wafer bonding, plating, warpage control, Python, R, SQL, Visual Basic, E3, FDC, RMS
Technologies
Python, R, SQL, Visual Basic, E3, FDC, RMS
Responsibilities
Establish and improve wafer level process conditions and technologies, upgrade process capabilities to reduce production costs, evaluate and promote new equipment and materials, ensure defense coverage through process and testing, conduct continuous data analysis for advanced controls, coordinate technology development strategies with cross-functional teams, provide Process Of Record (POR) and Model Of Record (MOR) documentation for product transfer
Seniority
Senior, hands-on IC
