Silicon Design-for-Test (DFT) Engineer
Core
Design and implement Design-for-Test (DFT) solutions for high-performance silicon (SERDES PHY, compute, memory, connectivity) to ensure functional accuracy and performance for AGI compute platforms.
Role type
Silicon DFT Engineer
Builds
High-performance silicon for AGI compute, memory, and connectivity
Domain
Semiconductor / Hardware / AGI Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
DFT implementation (MBIST, at-speed scan, scan compression), JTAG/IEEE 1149.1, IJTAG/IEEE 1687, Streaming Scan Networks (SSN), PHY firmware loading/validation (SPI/I2C/JTAG), SoC-level DFT integration, ATPG pattern generation, scan chain closure, root cause analysis for test escapes
Preferred skills
System-level DFT access (hierarchical, multi-die/chiplet), EDA tools (Synopsys DFT Compiler, Mentor Tessent)
Technologies
Synopsys DFT Compiler, Mentor Tessent, SPI, I2C, JTAG, IEEE 1149.1, IEEE 1687
Responsibilities
Design functional test solutions for SERDES PHY; Integrate PHY IP blocks with DFT interfaces; Develop firmware loading flows for PHY bring-up; Collaborate on silicon test program development from simulation to ATE; Execute DFT implementation and verification flows; Support test escapes root cause analysis
Seniority
Mid to Senior, hands-on IC
