IC packaging layout manager
Core
Manage the IC packaging layout team for high-speed 2D and 2.5D packages, driving New Product Introduction (NPI) from concept to mass production.
Role type
Senior IC packaging layout manager
Builds
High-speed semiconductor packages (2D/2.5D) for data infrastructure, enterprise, cloud, and AI applications
Domain
Semiconductor packaging and high-speed interface design
Required skills
IC package layout tools (Cadence APD, Mentor XPD), 2.5D package design (CoWOS), high-speed SerDes interfaces (224 Gbps), die-to-die and HBM interfaces, RDL interposers, NPI process management, constraint manager setup, layout automation (scripting/AI), DFM process, power plane design, vendor management
Preferred skills
Master's/PhD in CS/EE, experience with packaging materials and substrate design rules
Technologies
Cadence APD, Mentor XPD, CoWOS, SerDes, HBM, RDL
Responsibilities
Manage team for IC package layout across multiple product lines, develop team expertise in manufacturing tolerances, manage resources for layouts, automate layout tasks, ensure team well-being and efficiency
Seniority
Senior, hands-on IC
