Staff/Senior Staff Physical Verification CAD engineer
Core
Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation to ensure the integrity of semiconductor products.
Role type
Senior Staff IC physical verification CAD engineer
Builds
Automated physical verification flows, design rule decks, and validation procedures for SOC tape-out
Domain
Semiconductor / IC Design / EDA
Required skills
CAD and EDA tool development, DRC and LVS debugging, Tcl scripting, Perl scripting, Python scripting, Synopsys ICV, Calibre svrf/tvf, full custom layout tools, design flow optimization, tool integration, foundry interface management
Preferred skills
Mentor Calibre svrf/tvf, third-party EDA tool evaluation, cross-functional technical guidance
Technologies
Cadence, Synopsys, Mentor Graphics, Tcl, Perl, Python, Calibre, ICV
Responsibilities
Develop run sets for nanotechnology and support Calibre/ICV for DRC/LVS debugging; Automate physical verification flow and design rule decks; Integrate EDA tools into cohesive design flows; Define and optimize design methodologies from physical verification to SoC tapeout; Monitor and optimize tool performance and reliability; Create documentation and training materials for CAD/EDA tools
Seniority
Senior Staff, hands-on IC with leadership
