Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity
Core
Senior technical authority ensuring Signal Integrity (SI) and Power Integrity (PI) for customer platforms built on Marvell's Ethernet Switch and UALink silicon, from prototype through mass production.
Role type
Senior Principal Hardware Application Engineer (Signal & Power Integrity)
Builds
High-speed networking and AI infrastructure platforms (Ethernet switches, UALink)
Domain
Semiconductor hardware, high-speed SerDes, data center networking
Required skills
Signal integrity (SI), Power integrity (PI), high-speed SerDes design (25G to 224G PAM4), post-silicon channel extraction, PDN simulation, lab characterization (VNAs, BERTs, oscilloscopes), EDA toolchains (Ansys, Cadence), customer technical leadership, training delivery
Preferred skills
Ethernet switch platform experience, open AI fabric standards, ODM/CM design flows, SerDes tuning methodology definition, chip-to-module ecosystem knowledge
Technologies
Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, VNAs, BERTs, real-time scopes, TDR, jitter analyzers, compliance test kits
Responsibilities
Define and maintain layout/routing guidelines for high-speed channels and PDNs; perform post-silicon extraction and simulation; lead compliance testing and lab characterization; provide SerDes tuning guidance; run PI simulations for PDN impedance and IR drop; translate customer constraints into silicon feedback; engage ODMs on design reviews and qualification; support reference design validation; deliver SI/PI training to customers and internal teams; provide technical leadership for 112G/224G/448G systems.
Seniority
Principal, hands-on IC with strategic influence
