Physical Design Intern - Master's Degree
Citizens or permanent residents only
Core
Transform RTL designs into manufacturing-ready GDS for leading AI infrastructure and ASIC chips.
Role type
Physical Design Intern
Builds
Next-generation high-performance AI computing solutions (SOC designs)
Domain
Semiconductor / ASIC / AI Infrastructure
Required skills
Tcl/Tk/Perl/Python scripting, Static Timing Analysis, Physical Synthesis, Power/IR/EM analysis, LVS/DRC/ERC/ANT verification, Block-level layout implementation
Preferred skills
Automatic place and route (Synopsys/Cadence), Synthesis/STA experience
Responsibilities
Block-level layout implementation and timing closure, Static Timing/Crosstalk Analysis, Synthesis/Physical Synthesis, Power/IR/EM analysis, Physical verification (LVS/DRC/ERC/ANT), ECO implementation
