Principal Advanced Packaging Design Engineer
Core
Lead package design and technology development for next-generation HPC, AI, and networking solutions, focusing on signal, power, thermal, and mechanical integrity of multi-chip configurations.
Role type
Principal Advanced Packaging Design Engineer
Builds
High-performance 2.5D/3D packages, co-packaged copper/optical solutions, and advanced substrates for data infrastructure.
Domain
Semiconductor packaging, High-Performance Computing (HPC), Artificial Intelligence (AI), Networking
Deliverable
production ML models | product features
Required skills
Advanced packaging architecture (2.5D/3D), substrate/board design, DFM and reliability principles, signal/power integrity analysis, multi-chip integration, trade-off decision making
Preferred skills
HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIe, Ethernet expertise, thermal-mechanical vehicle design, tool development
Technologies
Cadence 3DIC, ISP, APD, SiP, Sigrity, Clarity, Innovus, Virtuoso, Ansys, AutoCAD, SolidWorks
Responsibilities
Lead small project teams to deliver packaging solutions, drive package definition and architecture for performance/thermal vehicles, interface with suppliers to ensure manufactability and performance
Seniority
Principal, hands-on IC with strategic leadership
