Analog Layout Intern, BS - Summer 2027
Based in United States
Core
Translate analog IC schematics into physical layout using Cadence Virtuoso and run physical verification flows (DRC, LVS) to ensure design integrity for next-generation semiconductor IP.
Role type
Analog Layout Engineer Intern
Builds
Analog IC layouts and semiconductor IP for Automotive, Storage, Security, and Networking business units
Domain
Semiconductor / Analog IC Design
Required skills
Analog circuit theory, Microelectronics, IC layout, VLSI design, EDA tools (Cadence Virtuoso, Calibre)
Responsibilities
Translate analog IC schematics into physical layout, Run design rule checks (DRC) and layout versus schematic (LVS), Collaborate with Analog IC Designers to refine and debug layouts, Present technical findings to cross-functional global teams
Seniority
Intern