Analog Layout Intern, BS - Summer 2027
Core
Translate analog IC schematics into physical layout and run physical verification flows to ensure design integrity for next-generation semiconductor IP.
Role type
Analog Layout Engineer Intern
Builds
Analog IC layouts and semiconductor IP for Automotive, Storage, Security, and Networking business units
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog circuit theory, Microelectronics, IC layout, VLSI design, EDA tools (Cadence Virtuoso, Calibre)
Preferred skills
Experience with advanced process nodes (TSMC N2/N3)
Technologies
Cadence Virtuoso, Calibre, TSMC N2/N3
Responsibilities
Translate analog IC schematics into physical layout, Run design rule checks (DRC) and layout versus schematic (LVS), Collaborate with Analog IC Designers to refine and debug layouts, Present progress updates to cross-functional global teams
Seniority
Intern