Physical Design Engineer Intern, MS - Summer 2027
Core
Intern role performing synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks for next-gen cloud, AI, storage, and networking chips.
Role type
Physical Design Engineer Intern
Builds
ASIC and processor designs for data center and networking solutions
Domain
Semiconductor / VLSI / Chip Design
Required skills
Synthesis, floor planning, place and route, clock insertion, timing analysis, timing closure, Python scripting, TCL scripting, Perl scripting, Shell scripting, Unix environment usage, EDA tools (PrimeTime, Tempus), CAD tools, RTL synthesis, Verilog, SystemVerilog
Preferred skills
Strong analysis, problem solving
Technologies
Synopsys PrimeTime, Cadence Tempus, Mentor, Python, TCL, Perl, Shell, Unix
Responsibilities
Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks; Write scripts in Python, TCL, Perl, and Shell to aid design and development activities; Utilize problem solving skills to analyze, debug, and implement fixes for design violations using CAD tools; Collaborate with RTL, Synthesis, and other Design teams to resolve congestion & timing bottlenecks
Seniority
Intern
