Physical Design Engineer Intern, MS - Summer 2027
Core
Intern role focused on physical design of ASIC and processor designs, performing synthesis, floor planning, place and route, and timing closure for next-gen data center chips.
Role type
Physical Design Engineer Intern
Builds
ASIC and processor designs for cloud, AI, storage, and networking solutions
Domain
Semiconductor / VLSI / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Synthesis, floor planning, place and route, clock insertion, timing analysis, timing closure, Python scripting, TCL scripting, Perl scripting, Shell scripting, Unix environment usage, CAD tools debugging
Preferred skills
VLSI coursework, digital logic, circuit design, computer architecture, RTL synthesis, Verilog, SystemVerilog, static timing analysis, digital systems, microelectronics
Technologies
PrimeTime, Tempus, Synopsys, Cadence, Mentor
Responsibilities
Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks; Write scripts in Python, TCL, Perl, and Shell to aid design and development; Analyze, debug, and implement fixes for design violations using CAD tools; Collaborate with RTL, Synthesis, and other Design teams to resolve congestion and timing bottlenecks
Seniority
Intern