Ph.D. Intern - Advanced Packaging & Physical Integration
Core
Ph.D. intern solving advanced packaging design, signal integrity, and thermal/mechanical simulation challenges for production AI accelerators and high-speed connectivity platforms.
Role type
Ph.D. intern, advanced packaging & physical integration
Builds
Custom XPUs, AI accelerators, and high-speed connectivity platforms for hyperscalers
Domain
Semiconductor industry, advanced packaging, electrical engineering, materials science
Deliverable
production ML models | product features
Required skills
semiconductor packaging research, signal/power integrity analysis, thermal-mechanical simulation, 2.5D/3D chiplet integration, substrate/interposer design, high-speed interconnect characterization, electromagnetics, heat transfer, materials mechanics, EDA/simulation tools (Ansys, Cadence Sigrity)
Preferred skills
high-speed serial interface SI analysis (100G+/lane), CoWoS/FOPLP/RDL interposers/flip-chip BGA familiarity, co-packaged optics (CPO) integration, power delivery network (PDN) design, design-for-manufacturing (DFM)
Technologies
Ansys HFSS, Ansys Icepak, Cadence Sigrity
Responsibilities
Perform SI/PI analysis for 224G SerDes and HBM interfaces; develop thermal/mechanical simulation models for chiplet packages; contribute to physical design and layout of package substrates and interposers; collaborate with chip design/assembly/test teams to validate packaging assumptions; use EDA tools to model/optimize package performance; present analysis results and design recommendations
Seniority
Ph.D. candidate, research-focused IC
