Staff Engineer, Physical Design
Core
Staff Engineer responsible for physical design and methodology of next-generation high-performance processor chips in leading-edge CMOS processes for server, 5G/6G, and networking applications.
Role type
Staff IC Physical Design Engineer
Builds
Custom Processor/ASIC solutions and data infrastructure IP
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features
Required skills
Block-level PNR for advanced CMOS nodes (7nm/5nm), Synthesis, Place & Route, Static Timing Analysis, Timing Closure, ECO development, Scripting (Tcl/Perl/Makefile)
Preferred skills
Physical verification, Formal verification
Technologies
Cadence Genus, Innovus, Synopsys IC Compiler, Fusion Compiler, Tempus, PrimeTime, Voltus, PrimeRail, Calibre, LEC, Formality
Responsibilities
Maintain and enhance Place and Route Flow, perform synthesis/place/route/timing analysis on complex logic blocks, develop timing and logic ECOs, debug block-level timing issues at partition level
Seniority
Staff, hands-on IC with strategic impact
