Sr Staff Design Verification Engineer
Core
Building and validating a highly programmable in-memory computing architecture for AI applications from cloud to edge.
Role type
Sr Staff Design Verification Engineer
Builds
In-memory computing architecture for AI
Domain
Hardware/ASIC design verification for AI
Deliverable
production ML models
Required skills
UVM/OVM methodologies, SystemVerilog (randomization, coverage, assertions), ASIC-SoC verification, IP/SoC verification cycle, debug experience
Preferred skills
C/C++, tape-out experience, multiple verification environment implementation
Technologies
SystemVerilog, UVM, OVM
Responsibilities
Lead verification from concept to tape-out to bring-up, develop verification environments, debug ASIC-SoC designs, ensure coverage and assertion compliance
Seniority
Sr Staff, hands-on IC
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