Senior Manager, DFT
Core
Leading and managing DFT methodology teams to deliver flows and solutions for complex IP and SoC designs in the Custom/Compute space.
Role type
Senior Manager, Design-for-Test (DFT)
Builds
DFT/DFX features, validation, IP-DFT, and post-silicon bringup/debug for Custom/Compute ASIC/SoC designs.
Domain
Semiconductor, Custom/Compute ASIC/SoC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT flows and methodologies, DFT toolsets (Siemens Tessent, Spyglass/Tmax, DC, Genus, Modus), DFT methodology development (SCAN-Insertion, MBIST, ATPG, Validation, STA, IP-DFX, Post-Silicon Bringup/Debug), scripting (PERL, Tcl-tck, C-Shell), Digital Circuit Design fundamentals, Logic Design
Preferred skills
ASIC design experience, AI adoption
Technologies
Siemens Tessent, Spyglass, Tmax, DC, Genus, Modus, PERL, Tcl-tck, C-Shell
Responsibilities
Lead and manage DFT methodology team responsible for flows and solutions on complex IP and SoC; Drive DFT methodology development and support for DFT/DFX features, validation, and post-silicon bringup/debug; Manage, mentor, and guide a small team of engineers enabling scaling across multiple designs; Define and enhance DFT methodologies and tools to benchmark and enable new domain innovations.
Seniority
Senior Manager, hands-on leadership
