Principal Design Verification Engineer
Core
Architecting and developing functional verification environments, reference models, and bus-functional monitors for high-speed data transfer chips serving telecom and automotive markets.
Role type
Principal Design Verification Engineer
Builds
Production verification environments and tools for multi-core SoCs
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Python, Perl, C++, ARM assembly, Object-Oriented Design, Linux OS, networking protocols
Preferred skills
Random verification techniques, coverage analysis, boot code verification, EDA Verification tools
Technologies
System Verilog, UVM, Python, Perl, C++, ARM assembly, Linux
Responsibilities
Develop verification environment architecture and reference models; Write verification test plans using random techniques; Debug failures and resolve issues with designers; Verify boot code and maintain verification tools; Transform engineering requirements into scalable software tools; Perform unit and regression testing of software tools
Seniority
Principal, hands-on IC with strategy & mentorship
