Senior Staff Digital Design Engineer
Core
Senior Staff Digital ASIC Design Engineer developing high-performance connectivity silicon for AI scale data centers, focusing on digital pipelines, high-speed datapaths, and DSP-driven processing engines.
Role type
Senior Staff IC Digital ASIC Design Engineer
Builds
High-performance connectivity ASICs for Ethernet and optical interconnects serving hyperscalers
Domain
Semiconductor / Data Center Connectivity / High-Speed Networking
Deliverable
production ML models | product features
Required skills
Digital ASIC design, Micro-architecture development, SystemVerilog RTL, High-performance DSP design, High-speed datapath design, Ethernet protocols, Front-end design flows (lint, CDC/RDC, synthesis, STA), Advanced process nodes (5nm/3nm), Debug skills (RTL simulation, emulation, FPGA, silicon bring-up), Leadership and mentoring
Preferred skills
Advanced high-speed DSP algorithm implementation (adaptive equalization, channel estimation), FEC architectures (LDPC, RS, BCH), PHY design experience (PMA-level, SerDes-adjacent logic)
Responsibilities
Define SoC-level specifications and micro-architecture for complex subsystems; Develop synthesizable SystemVerilog RTL for assigned blocks; Drive full ASIC front-end design flow including timing closure and design-for-test; Lead integration of digital logic into larger subsystems; Develop scalable design components and reusable infrastructure; Collaborate with DV teams on verification strategies and validation; Support pre-silicon validation via emulation and FPGA prototyping; Drive post-silicon bring-up and debug; Participate in design reviews and methodology improvements
Seniority
Senior Staff, hands-on IC with technical direction
