Senior Front End Design Engineer (Microarchitecture)
Core
Designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE), focusing on high-performance, power-efficient, and scalable semiconductor architectures.
Role type
Senior IC front-end design engineer (microarchitecture)
Builds
Cerebras Wafer Scale Engine (WSE) systems
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
RTL design and integration, Functional Specification, Micro-architecture, Synthesis, Physical Design (PD) collaboration, Design Verification (DV) collaboration, DFT collaboration, Silicon debugging, Networking stack (TCP/IP, RDMA, Ethernet), PCIe/CPU interfaces, Serdes technology, Python/TCL scripting
Preferred skills
FPGA development toolchain (Place and Route, Floor planning, Timing Analysis), Managing external ASIC vendors
Technologies
Python, TCL, FPGA toolchains
Responsibilities
Drive all aspects of chip design including Functional Specification, Micro-architecture, RTL development, and Synthesis; Collaborate with PD teams for design closure to meet PPA goals; Work with DV and DFT teams for functional and test coverage; Debug silicon-level functional, timing, and power issues during bring up
Seniority
Senior, hands-on IC
