Sr. Staff Verification Engineer
Core
Ensuring functional correctness of complex SoCs and IP by defining verification strategies and developing robust UVM environments for next-generation optical interconnect technology.
Role type
Sr. Staff Verification Engineer (SoC/IP)
Builds
Optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB) for AI accelerators and GPUs
Domain
Semiconductor / Photonic Fabric / AI Infrastructure
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM methodology, constrained random verification, coverage-driven techniques, Python scripting, Xcelium/Questa/VCS simulators, object-oriented design
Preferred skills
AMBA protocols (AXI/AHB/APB), PCIe, Ethernet, I2C, SPI, UART, ARM/processor subsystem verification, NoC, cache designs, C/C++ for reference modeling, gate-level simulation, post-silicon validation debug, mentoring
Technologies
SystemVerilog, UVM, Python, Xcelium, Questa, VCS, C/C++
Responsibilities
Develop SystemVerilog/UVM verification environments for complex SoCs from block-level IPs through full-chip integration; Create detailed verification plans ensuring comprehensive functional and code coverage; Architect UVM testbenches including stimulus generators, scoreboards, and constrained random sequences; Collaborate with design, architecture, and software teams to manage milestones; Drive continuous improvement of verification methodologies and processes; Build and optimize verification infrastructure regression frameworks and automation; Lead rigorous testbench reviews; Coordinate with software and emulation teams for tapeout success; Use leading edge AI tools to develop infrastructure
Seniority
Sr. Staff, hands-on IC with strategy & mentorship
