DFT Principal Engineer
Core
Lead Physical Design for Test (DFT) for Power Management ICs including DC-DC PMIC, controllers, and drivers for consumer, industrial, and automotive applications.
Role type
Principal Physical DFT Engineer
Builds
Power management chips (PMIC, controllers, drivers)
Domain
Semiconductor / Power Management / ASIC Design
Required skills
Scan implementation (Stuck-At, MBIST, iJTAG, BSCAN, Transition, bridge faults), Timing constraints for scan modes, Pattern simulation (zero delay, SDF), Coverage analysis, Low power issue resolution, Post-silicon debug, Verilog, TCL, Perl, Python, XML
Preferred skills
Flow improvement for PPA impact, Complex IC release track record
Technologies
Verilog, TCL, Perl, Python, XML, SDF, iJTAG, MBIST, BSCAN
Responsibilities
Lead DFT implementation, Provide timing constraints for scan modes, Perform pattern simulation and coverage analysis, Fix low power issues post-DFT, Conduct post-silicon debug, Improve existing DFT flow for PPA
Seniority
Principal, hands-on IC development and team leadership
