Staff STA Engineer
Core
Staff STA Engineer leading timing closure and signoff for complex multi-power domain digital ICs (PMIC, controllers, drivers) across consumer, industrial, and automotive applications.
Role type
Staff STA Engineer (Digital IC Design)
Builds
Power management ICs (PMIC, DC-DC, AC-DC, LED drivers, SiC drivers, switches, efuses)
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Required skills
Static Timing Analysis (STA), timing constraint handling, ECO generation, timing regression, P&R signoff, LEC, Low Power checks, Verilog, TCL, Perl, Python, XML
Preferred skills
Power recovery, flow improvement, PPA optimization
Technologies
I2C, DDR, USB, UPF, CDC, ASIC synthesis, P&R
Responsibilities
Lead STA for full-chip IO protocols (I2C, DDR, USB), generate ECOs for timing closure, run STA regression across high mode/corner counts, debug timing constraints in P&R, perform LEC and low-power checks.
Seniority
Staff, hands-on IC design leadership
