Senior Mixed Signal DV Engineer
Core
Confirm accuracy of analog and mixed-signal electronic designs and components before pattern generation/mask development; analyze equipment, run simulations, and evaluate test results to ensure adherence to specifications.
Role type
Senior IC design verification engineer (mixed-signal)
Builds
Custom IC system solutions including display power, charger power, camera PMICs, and high-performance communication interfaces
Domain
Semiconductor / Mixed-signal analog and digital IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog-AMS, Verilog-A, Wreal (RNM), EENet, Cadence simulation tools (Xcelium, vManager, JasperGold), Cadence Virtuoso, AMS Designer, Formal Property Verification (FPV), Clock Domain Crossing (CDC) assertions, Reset Domain Crossing (RDC) assertions, UPF (Unified Power Format), I2C, SPI, UART, ASI protocols, RTL/Gate-Level simulation, regression management, coverage tracking
Preferred skills
Python/Perl/Shell scripting, AI/ML-driven verification methodologies, signal processing, PMICs, high-speed communication interfaces, silicon debug, post-silicon integration
Technologies
SystemVerilog, UVM, Verilog-AMS, Verilog-A, Wreal, EENet, Cadence Xcelium, Cadence vManager, Cadence JasperGold, Cadence Virtuoso, AMS Designer, Python, Perl, Shell, UPF, I2C, SPI, UART, ASI
Responsibilities
Drive verification strategy and create detailed test plans with coverage metrics; Lead ground-up development of UVM-based verification environments; Build mixed-signal testbenches combining schematics, behavioral models, and RTL; Create high-fidelity analog behavioral models for top-level simulation; Implement analog checkers and assertions; Execute RTL and Gate-Level Simulations and manage regressions; Resolve complex design and testbench issues using advanced debugging; Support ATE functional pattern generation and silicon characterization
Seniority
Senior, hands-on IC