Senior Analog Mixed Signal DV Engineer
Core
Develop coverage-driven verification strategies and high-fidelity analog behavioral models for custom mobile electronics power and communication ICs.
Role type
Senior IC analog mixed-signal verification engineer
Builds
Custom mobile electronics power management and communication interface ICs
Domain
Semiconductor / Analog Mixed-Signal Design
Deliverable
production ML models | product features
Required skills
Verilog-AMS, Verilog-A, Wreal, EENet, Cadence Virtuoso/AMS Designer, RTL simulation, Gate Level Simulation, functional coverage analysis, analog checkers, post-processing strategies
Preferred skills
SystemVerilog, UVM, Python, Perl, Shell scripting, AI-driven verification methodologies, silicon debug, I2C, SPI, UART, ASI protocols
Technologies
Cadence Virtuoso, AMS Designer, Verilog-A, Verilog-AMS, Wreal, EENet, SystemVerilog, UVM, Python, Perl, Shell
Responsibilities
Develop detailed coverage-driven Verification Plans; Create high-fidelity analog behavioural models; Build and enhance mixed signal testbenches; Implement real-time analog checkers and post-processing checker strategies; Execute RTL and Gate Level Simulations; Collaborate with Digital DV, Analog Designers, and Post-Silicon Validation teams
Seniority
Senior, hands-on IC