Layout Designer | PMIC
Core
Designing power management ICs for high power density applications with a focus on thermal and electrical performance.
Role type
Senior IC layout engineer (analog/power)
Builds
Power management ICs
Domain
Semiconductor / Analog Power ICs
Required skills
Analog and power layout techniques, High-voltage design rules, Parasitic-aware layout, Layout tools (Cadence Virtuoso), DRC/LVS/PEX flows, Power device layout (LDMOS, MOSFETs, ESD)
Preferred skills
Adoption of new tools and flows, Analytical problem-solving
Technologies
Cadence Virtuoso, DRC, LVS, PEX
Responsibilities
Execute hands-on layout for analog and power blocks, Collaborate with circuit designers to deliver high-quality layouts, Manage thermal and electrical performance constraints, Adopt new design tools and processes
Seniority
Senior, hands-on IC
