SoC Design Verification Engineer (Up to Principal Level)
Core
Verify complex SoC, subsystem, and IP designs through planning, testbench development, simulation, coverage closure, and debug to ensure pre-silicon release readiness.
Role type
SoC Design Verification Engineer (IC)
Builds
Verified SoC designs, subsystems, and IP blocks for Qualcomm products
Domain
Semiconductor / Hardware Design Verification
Required skills
SystemVerilog, UVM, simulation, regression, waveform debug, functional coverage, digital design fundamentals, RTL, FSMs, protocols, clock/reset behavior, SoC architecture, scripting (Python/Perl/Tcl/Shell)
Preferred skills
AMBA protocols (AXI, AHB, APB), formal verification, assertion-based verification, CDC/RDC analysis, emulation, FPGA prototyping, gate-level simulation, power-intent verification, EDA tools, technical leadership
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, Shell, EDA tools, FPGA, Emulation
Responsibilities
Translate specifications into verification plans and signoff criteria; Develop and maintain SystemVerilog/UVM testbenches and reusable components; Create directed, constrained-random, and coverage-driven tests; Verify RTL integration, interfaces, power management, and interconnect; Run and debug simulation, regression, formal, and emulation flows; Analyze failures and perform root-cause debug; Define and close coverage metrics; Collaborate with RTL, architecture, and synthesis teams; Develop automation scripts; Document verification plans and results.
Seniority
Up to Principal, hands-on IC with strategy & mentorship
