Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer)
Core
Drive design, implementation, and optimization of advanced low-power SoCs, focusing on physical verification, EM/IR drop analysis, and fixing floorplan & power grid issues.
Role type
Senior IC Physical Design Engineer (Physical Verification & Power Integrity)
Builds
Low-power System-on-Chips (SoCs) for IoT, automotive, and consumer electronics
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC physical design, Physical Verification (DRC, LVS, PERC), EM/IR drop analysis, Power analysis, EDA tool automation, GDS streamout, PG fill insertion, Foundry collaboration
Preferred skills
Chip-level integration, Hierarchical design, Static Timing Analysis (STA), Low-power techniques (UPF/CPF, power gating, DVFS), Cross-site collaboration
Technologies
Cadence Innovus, Voltus, Pegasus, Mentor-Calibre
Responsibilities
Lead end-to-end low power & physical verification flow; Run power analysis and define EM analysis strategies; Debug grid weakness and provide solutions; Collaborate with Floorplan, PnR, and packaging teams; Drive EDA tool automation; Mentor junior engineers; Work with foundries on tape-out readiness
Seniority
Senior, hands-on IC
