Senior Power Integrity (PI) Analysis Engineer
Core
Own IR-drop sign-off and power grid implementation for high-performance CPU blocks to ensure robust voltage margins.
Role type
Senior Power Integrity (PI) Analysis Engineer
Builds
High-performance CPU blocks and SoC-level power delivery models
Domain
Semiconductor physical design / Power Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IR-drop analysis (static and dynamic), power grid implementation, package modeling, bump/ball map configuration, power grid architecture definition, CPM model development, PI methodology documentation
Preferred skills
Collaboration with physical design, package, board, and PMIC teams
Technologies
CPM models, PI analysis environments
Responsibilities
Own block-level IR drop sign-off and power grid implementation; Set up PI analysis environments; Define power grid requirements; Drive power grid architecture decisions; Deliver CPM models for SoC integration; Develop and champion advanced PI methodologies; Collaborate with cross-functional teams for end-to-end power delivery
Seniority
Senior, hands-on IC
