Advanced Packaging Layout Engineering Team Leader (Substrate & Interposer) (Hybrid)
Core
Lead and support the San Jose package layout team, providing hands-on technical guidance and mentorship for advanced ASIC packaging and CoWoS projects.
Role type
Senior IC packaging layout team leader
Builds
Complex ASIC advanced packaging solutions (substrates, interposers, CoWoS)
Domain
Semiconductor / Advanced Packaging
Required skills
Package layout design, High-speed routing, Power distribution networks (PDN), EDA tools, Cadence APD+, Substrate layout, Interposer design, Escape routing, SI/PI collaboration, Team leadership, Resource coordination
Preferred skills
Mentoring layout engineers, ASIC package substrate implementation, Vendor management, Scripting (Python, Perl, TCL)
Technologies
Cadence APD+, Python, Perl, TCL
Responsibilities
Lead and support the San Jose package layout team, Drive hands-on package layout activities for complex ASIC advanced packaging, Collaborate with package leads, SI/PI teams, and manufacturing partners, Coordinate layout resource allocation and staffing, Support optimization of package pinouts and CoWoS interposers, Contribute to hiring and development of layout engineering talent
Seniority
Senior, hands-on IC with team leadership
