Senior ASIC DFT DV Engineer (Hybrid)
Core
Develop test benches and MBIST methodologies to verify DFT architecture for Cisco's core Switching, Routing, and Wireless silicon platforms.
Role type
Senior ASIC DFT DV Engineer
Builds
Hardware platforms for AI-era networking products
Domain
Semiconductor / Networking
Required skills
DFT architecture, MBIST methodology, RTL verification, memory architecture debugging, TCL/Python/Perl scripting, ATE screening, DVE/Verdi debugging
Preferred skills
Verilog/SystemVerilog, memory failure correlation, industry-standard DFT tools (Synopsys DesignWare, SMS, TestMax, Tessent)
Technologies
Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent, DVE/Verdi, TCL, Python, Perl, Verilog, SystemVerilog
Responsibilities
Test planning and development of test benches for DFT architecture, owning MBIST methodology across the portfolio, architecting reusable hierarchical infrastructures, collaborating with RTL and physical design teams
Seniority
Senior, hands-on IC
