ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)
Core
Develop, document, and implement design rules for ultra-high-speed signaling and analyze substrate signal/power integrity for next-generation ASIC packaging deployed in Cisco platforms.
Role type
Senior IC ASIC Packaging Signal/Power Integrity Hardware Engineer
Builds
High-performance Silicon ASICs for unified routing and switching portfolios (TOR switches to web-scale data centers)
Domain
Semiconductor / High-Speed Digital Design / Advanced Packaging
Required skills
High-speed design principles (Transmission Line Theory, electromagnetics, S-parameters, impedance), SI/PI simulation (Cadence Sigrity, Ansys HFSS, Keysight ADS), Layout review & physical validation (Cadence APD, Ansys EM), SPICE circuit analysis, 56G PAM4 SerDes architectures, channel modeling, BER prediction
Preferred skills
High-bandwidth memory (HBM) interface SI, Die-to-die interfaces (UCIe), Advanced packaging (CoWoS, EMIB, interposer), Vector Network Analysis, IBIS
Technologies
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, 56G PAM4, UCIe, CoWoS, EMIB
Responsibilities
Develop and implement design rules for ultra-high-speed signaling; Analyze substrate signal integrity (SI) and power integrity (PI) across interposer, substrate, and PCB; Design and document ASIC packages for high-volume release including post-layout extraction; Collaborate with system partners and design leads to resolve complex technical issues
Seniority
Senior, hands-on IC
