ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years
Core
Develop high-quality Design-for-Test (DFT) verification strategies, test benches, and test plans for Cisco's silicon networking hardware to support ATE screening, in-system test, and debug.
Role type
Senior ASIC DFT/DV Engineer
Builds
Test logic and verification flows for unified silicon architecture (Cisco Silicon One) used in switches, routers, and wireless products.
Domain
Semiconductor hardware design and verification
Required skills
System Verilog, DFT architecture, test planning, ATE screening, in-system test, debug methodologies, Tcl, Python/Perl
Preferred skills
UVM, JTAG protocol, scan architecture, MBIST, boundary scan
Technologies
System Verilog, UVM, JTAG, MBIST, DVE/Verdi, Tcl, Python, Perl
Responsibilities
Collaborate with RTL and physical design teams on chip architecture; develop test benches for DFT verification; drive integration and validation of test logic; craft innovative DFT strategies for new silicon models.
Seniority
Senior, hands-on IC
