Senior ASIC DFT DV Engineer (Hybrid)
Core
Develop test benches and test planning for Design-for-Test (DFT) architecture to support ATE screening, in-system test, debug, and diagnostics for Cisco's switching, routing, and wireless silicon platforms.
Role type
Senior ASIC DFT/DV Engineer
Builds
Hardware platforms for core Switching, Routing, and Wireless products
Domain
Semiconductor / Hardware Design
Required skills
Test planning, System Verilog, DVE/Verdi debugging, TCL, Python, Perl
Preferred skills
UVM, JTAG protocol, scan architecture, MBIST, boundary scan
Technologies
System Verilog, DVE/Verdi, TCL, Python, Perl, JTAG, MBIST
Responsibilities
Develop test benches for DFT architecture; Collaborate with design and verification teams on test logic integration; Drive reusable test and debug methodologies for new silicon models; Debug efficiently and craft solutions.
Seniority
Senior, hands-on IC
