ASIC Design Verification Engineer
Core
Architect and develop Design Verification (DV) infrastructure for complex ASICs, ensuring robust verification coverage and seamless integration for Cisco's data center hardware platforms.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Block, cluster, and top-level DV environments and test plans for AI-era switching, routing, and wireless chips.
Domain
Semiconductor / ASIC Design / Data Center Infrastructure
Required skills
System Verilog, UVM methodology, constraint-random and directed stimulus, Perl scripting, Python scripting, RTL design qualification, Gate Level Simulation, emulation environment support
Preferred skills
Forwarding logic, P4, emulation platforms (Veloce, Palladium, Zebu, HAPS), formal verification tools, protocol knowledge (PCIe, CXL, Ethernet, RDMA, DDR, TCP)
Responsibilities
Architect and maintain DV infrastructure; build DV environments from scratch; develop and execute comprehensive test plans; ensure verification coverage; qualify RTL via Gate Level Simulations; debug post-silicon bring-up issues; support design testing in emulation environments
Seniority
Senior, hands-on IC
