ASIC Engineering Technical Leader
Core
Define, design, and verify high-performance ASIC subsystems for Cisco's core Switching, Routing, and Wireless products, focusing on high-speed mixed-signal architectures.
Role type
Senior IC ASIC Engineering Technical Leader
Builds
High-volume ASIC releases for AI and cloud infrastructure
Domain
Semiconductor / Analog and Mixed-Signal Circuit Design
Required skills
High-frequency CMOS circuit design, Custom analog and mixed-signal circuit design, Cadence Virtuoso CAD (layout, DRC, LVS, parasitic extraction), Programming (Skill, VerilogA, Tcl, Perl, Python, Matlab, C)
Preferred skills
High-speed wireline SerDes design, Signal processing, Digital design flow (synthesis, P&R), EM field simulation (EMX, Momentum, HFSS), Packaging technology, Measurement equipment, Project management tools
Technologies
Cadence Virtuoso, Skill, VerilogA, Tcl, Perl, Python, Matlab, C, Siemens/Mentor, Synopsys, EMX, Momentum, HFSS, Jira, SOS
Responsibilities
Oversee architecture and design of complex analog and mixed-signal circuits, Establish robust verification strategies, Collaborate with cross-functional teams to influence packaging and hardware requirements, Guide development of reusable code methodologies and physical design functions
Seniority
Senior, hands-on IC
