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ASIC DFT Engineer II Full Time - United States

San Jose, California, US💼 Full-time💰 $111,700–$111,700🗓 2026-09-16 → 2026-09-25

Core

ASIC Design for Test Engineer implementing DFT features for ATE, in-system test, debug, and diagnostics in AI-era switching, routing, and wireless products.

Role type

ASIC DFT Engineer

Builds

Hardware platforms for Cisco core Switching, Routing, and Wireless products

Domain

Semiconductor / ASIC Design / Hardware

Deliverable

production ML models | product features

Required skills

DFT implementation, automation scripting (Python/Tcl/Perl), SystemVerilog, ATPG, EDA tools, gate-level simulation debugging, JTAG protocols, scan architectures, BIST

Preferred skills

Verification skills, VLSI circuit physical behaviors, test timing validation, post-silicon validation

Technologies

TestMax, Tetramax, Tessent, PrimeTime, VCS

Responsibilities

Implement DFT features supporting ATE and diagnostics; Create and enhance automation scripts for implementation robustness; Collaborate with Design, DV, and Physical Design teams for test logic integration; Validate test timing and logic equivalency using SystemVerilog; Utilize ATPG and EDA tools for test pattern generation and analysis.

Seniority

Mid-level IC Engineer

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