ASIC Engineer
Core
Implementing Hardware Design-for-Test (DFT) features, developing DFT IP, and integrating testability into RTL for Cisco Silicon One networking hardware.
Role type
ASIC DFT Engineer
Builds
DFT IP, test logic, and debug strategies for silicon devices (bare die & stacked die) for enterprise and service provider networking products.
Domain
Semiconductor / Networking Hardware / ASIC Design
Deliverable
production ML models
Required skills
DFT implementation, Scan architecture, BIST (memory & boundary scan), JTAG protocols, ATPG, RTL integration, Gate level simulation, Debugging (via careerplan.io/jobs/2013978-asic-engineer-at-cisco)
Preferred skills
Post-silicon validation, ATE patterns, P1687, Tcl, Python, Perl
Technologies
TestMax, Tetramax, Tessent, PrimeTime, System Verilog, VCS
Responsibilities
Implement DFT features for ATE/in-system test, develop DFT IP, coordinate testability in RTL, validate test logic with design/PD teams, debug with simulators
Seniority
Mid-Senior, hands-on IC (4-8 years experience)
