ASIC DFT Engineer
Core
Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics for next-generation networking chips.
Role type
Senior IC ASIC DFT Engineer
Builds
Innovative silicon device models, bare die, and stacked die with re-usable test and debug strategies
Domain
Semiconductor / Networking Hardware
Deliverable
production ML models | product features
Required skills
DFT IP development, JTAG protocols, Scan and BIST architectures, ATPG, EDA tools (TestMax, Tetramax, Tessent, PrimeTime), Gate level simulation, VCS debugging, Post-silicon validation, ATE patterns, P1687
Preferred skills
Verilog design for custom DFT logic, DFT CAD development, Test Static Timing Analysis, System Verilog equivalence checking
Technologies
VCS, TestMax, Tetramax, Tessent, PrimeTime, P1687
Responsibilities
Implement DFT features for ATE and debug needs; Develop innovative DFT IP for full chip integration; Collaborate with RTL and PD teams on test logic validation; Drive DFT and quality processes through implementation and post-silicon phases; Craft solutions and debug with minimal mentorship
Seniority
Senior, hands-on IC
