ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Experience - 4 to 8 years
Core
Design and implement Hardware Design-for-Test (DFT) features for complex ASICs to support ATE, in-system test, debug, and diagnostics.
Role type
Senior ASIC DFT Hardware Engineer
Builds
Testable silicon chips for Cisco's core Switching, Routing, and Wireless products
Domain
Semiconductor / ASIC Design / Hardware Testing
Required skills
JTAG protocols, Scan insertion, ATPG, BScan, EDA tools (TestMax, Tetramax, Tessent), Gate level simulation, VCS debugging, Post-silicon validation, ATE patterns, P1687, Tcl/Python/Perl scripting
Preferred skills
Test Static Timing Analysis, Post silicon validation using DFT patterns
Technologies
VCS, TestMax, Tetramax, Tessent, P1687
Responsibilities
Implement DFT features for ATE and debug needs; Develop innovative DFT IP for full chip integration; Collaborate with design/verification/PD teams for test logic validation; Debug and craft solutions with minimal mentorship
Seniority
Mid-Senior, hands-on IC
