DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years
Core
Lead Hardware Design-for-Test (DFT) features for Cisco's silicon networking products, enabling ATE, in-system test, debug, and diagnostics.
Role type
Senior IC DFT Engineering Technical Lead
Builds
Innovative Hardware DFT IP and test/debug strategies for new silicon device models (bare die & stacked die)
Domain
Networking hardware / Silicon engineering / DFT
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture, ATPG, JTAG protocols, Scan and BIST (memory and boundary), EDA tools (TestMax, Tetramax, Tessent, PrimeTime), System Verilog, Gate level simulation, Debugging
Preferred skills
Post-silicon validation, ATE patterns (P1687), Scripting (Tcl, Python/Perl)
Technologies
TestMax, Tetramax, Tessent, PrimeTime, VCS, System Verilog, Tcl, Python, Perl
Responsibilities
Implement DFT features supporting ATE and diagnostics; Develop innovative DFT IP for full chip integration; Collaborate with design/verification/PD teams for test logic validation; Drive reusable test strategies for new silicon models; Debug solutions with minimal mentorship
Seniority
Senior, hands-on IC
