ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore
Core
Lead Design-for-Test (DFT) strategy and implementation for high-performance ASICs in Cisco's Silicon One architecture, collaborating with RTL and physical design teams to ensure testability and quality from conception to production.
Role type
Senior IC ASIC DFT Technical Leader
Builds
Next-generation networking chips (switching, routing, wireless) for enterprises, service providers, and public sector
Domain
Networking hardware / ASIC Design / Semiconductor
Required skills
DFT architecture (Scan, MBIST, JTAG), ATPG, EDA tools (TestMax, Tetramax, Tessent), Gate-level simulation, Timing closure, Tcl/Python/Perl scripting, Post-silicon validation
Preferred skills
Verilog design, Custom DFT logic development, DFT CAD development
Technologies
TestMax, Tetramax, Tessent, VCS, Tcl, Python, Perl
Responsibilities
Define DFT requirements early in the design cycle, manage reusable code and infrastructure, coordinate integration into PD and DV flows, lead technical expertise in physical design functions, interface with vendors on timing closure and electrical planning, develop test vehicles and perform verification
Seniority
Senior, hands-on IC
