Hardware Engineer
Core
Design advanced substrate and ASIC package layouts (BGA, flip-chip, SiP, multi-die) and HDI/mSAP PCBs for next-generation Cisco optical engines.
Role type
Senior IC ASIC Package Design Engineer
Builds
High-speed, robust, and manufacturable optical package solutions and PCBAs
Domain
Semiconductor hardware design / Optical networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence Allegro Package Designer, Cadence SiP Layout, substrate technologies, HDI design, stack-up implementation, high-speed signal routing, differential pair routing, DRC resolution, DFM analysis, multi-die integration
Preferred skills
Multi-year experience with organic substrates, interposers, 2.5D/3D stacking, XtractIM, PowerSI, HFSS, crosstalk mitigation, impedance control
Technologies
Cadence Allegro, Cadence SiP Layout, XtractIM, PowerSI, HFSS
Responsibilities
Create and maintain advanced substrate layouts for BGA, flip-chip, SiP, and multi-die packages; Perform substrate floor planning, bump/ball map implementation, and routing planning; Implement routing for high-speed signals, differential pairs, power, and ground networks meeting SI/PI constraints; Set up, review, and resolve package-level design rules, DRC violations, and manufacturability issues; Review DFM/DFT requirements and support fabrication, assembly, tape out, and package bring-up; Generate and maintain design release documentation, layout databases, and manufacturing output files; Participate in technical investigations, design reviews, and tradeoff discussions; Assist in developing and improving substrate/package layout methodologies and best practices
Seniority
Senior, hands-on IC
