ASIC Engineer
Core
ASIC verification engineer developing UVM-based verification environments for Cisco's Silicon One programmable architecture.
Role type
Senior IC ASIC Verification Engineer
Builds
Cisco Silicon One programmable architecture for future routing portfolio
Domain
Semiconductor / ASIC Design / Networking Hardware
Deliverable
production ML models | product features
Required skills
UVM, functional verification methodologies, RTL design, micro-architecture review, debug, root-cause analysis, post-silicon validation
Preferred skills
MATLAB simulations, bit-exact modeling, mixed-signal systems, Clock Domain Crossing (CDC)
Technologies
UVM, RTL, MATLAB
Responsibilities
Review micro-architecture specifications, Implement Verification environment UVM based, Collaborate with Design engineers to resolve bugs and achieve coverage closure, Work with the firmware/Lab teams to verify chip flows, Perform debug, root-cause analysis, and post-silicon validation in the lab
Seniority
Senior, hands-on IC
