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MBIST Technical Leader

San Jose, California, US💼 Full-time💰 $210,600–$210,600🗓 2026-07-01 → 2026-09-26

Core

Leading MBIST methodology and architecture for next-generation networking chips (Silicon One) to ensure silicon quality and yield.

Role type

Senior IC ASIC Technical Lead (MBIST)

Builds

Production ASICs for Cisco core Switching, Routing, and Wireless products

Domain

Semiconductor / Hardware / Networking

Deliverable

production ML models | product features

Required skills

ASIC DFT, memory architecture (SRAM, DRAM), industry-standard DFT tools, Python/TCL/Perl scripting, test strategy planning

Preferred skills

Verilog/System Verilog, memory failure correlation in production

Technologies

Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent

Responsibilities

Lead MBIST methodology, design and implement reusable MBIST architecture, define MBIST requirements for advanced technology nodes

Seniority

Senior, hands-on IC

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