MBIST Technical Leader

2 Locations💼 Full-time🗓 2026-07-01 → 2026-07-31

Required skills

Bachelors in Electrical engineering with at least 12+years (or Master's with 10+ years) of experience in ASIC DFT, Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes, Prior experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent), Scripting skills (Python, TCL, Perl) for automation of test generation and analysis, Strategic Skills: Ability to plan and execute complex test strategies, excellent communication skills for cross-team collaboration, and a focus on silicon quality and yield improvement

Preferred skills

Experience in Verilog/System Verilog, Experience addressing Memory failure correlation in production

Technologies

Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent, SRAM, DRAM

Responsibilities

Leading the MBIST methodology in silicon one chips, Design & implement robust and reusable MBIST architecture, Spec comprehensive MBIST architecture and implementation agnostic to technology and tools, MBIST requirement definition for advanced technology nodes & advanced tech packages

Seniority

Technical Lead

Domain

ASIC DFT, Memory architectures, Silicon One, Networking chips

Rewrite

## Responsibilities - Leading the MBIST methodology in Silicon One chips. - Designing and implementing robust and reusable MBIST architecture. - Specifying comprehensive MBIST architecture and implementation agnostic to technology and tools. - Defining MBIST requirements for advanced technology nodes and advanced tech packages. ## Requirements - Bachelor's in Electrical engineering with at least 12+ years (or Master's with 10+ years) of experience in ASIC DFT. - Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes. - Prior experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent). - Scripting skills (Python, TCL, Perl) for automation of test generation and analysis. - Strategic skills: Ability to plan and execute complex test strategies, excellent communication skills for cross-team collaboration, and a focus on silicon quality and yield improvement. ## Nice to Have - Experience in Verilog/System Verilog. - Experience addressing Memory failure correlation in production. ## Benefits - Starting salary range for U.S. and/or Canada locations: $210,600.00 to $305,100.00. - Benefits include medical, dental, vision insurance, 401(k) plan with matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. - Paid time away includes 10 paid holidays, 1 floating holiday, 1 birthday day off, 4 personal wellness days, 16 paid vacation days, 80 sick days, and optional volunteer days. - Annual bonuses for non-sales roles. - Performance-based incentive pay for sales roles. ## Company Info - Cisco is revolutionizing how data and infrastructure connect and protect organizations in the AI era. - The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products. - The role is part of the Silicon One development organization, involved in crafting cutting edge next generation networking chips. ## Message to Applicants - The application window is expected to close on: 09/01/2026. The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

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