ASIC DFT STA Engineer
Required skills
Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development Prior working experience in timing constraint development and verification Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile
Preferred skills
Masters degree + 10 years of relevant experience Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime Prior working experience with synthesis tools: Synopsys Fusion/design Compiler Prior working experience with Tessent tool like DFT insertion in RTL
Technologies
Synopsys TCM/Primetime, Synopsys Fusion/design Compiler, Tessent tool, SDC, RTL design, CDC/RDC, conformal verification, timing constraints, timing closure, DFT modes, scan shift/capture, BIST, Perl, TCL, Python, Makefile
Responsibilities
Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs Check timing for unconstrained endpoints, no clock, etc. Your role may include SDC validation, CDC check, and SDC flow development Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy
Seniority
Not specified
Domain
ASIC design, DFT, STA, networking chips, silicon, hardware platforms, AI, Cisco products
