Director, Physical Design & CAD Methodology (ASIC/SoC)
Core
Define global physical design methodology strategy and architect advanced CAD flows for high-performance ASIC/SoC designs.
Role type
Director, Physical Design & CAD Methodology
Builds
Silicon platforms for Cisco core Switching, Routing, and Wireless products
Domain
Semiconductor hardware design (ASIC/SoC) at advanced process nodes
Deliverable
production ML models | product features | infrastructure
Required skills
ASIC/SoC physical design, CAD methodology, hierarchical design, multi-die/chiplet integration, EDA tool suites, scripting (Tcl/Python/Perl), PDK integration, static timing analysis, physical verification
Preferred skills
AI/ML-driven EDA features, advanced process geometries (7nm/5nm/3nm/2nm), RTL-to-GDSII flows, power integrity analysis
Technologies
Innovus, Fusion Compiler, PrimeTime, Calibre, Tcl, Python, Perl
Responsibilities
Define global physical design methodology strategy, architect and deploy advanced CAD flows, manage and mentor a high-performing team, allocate engineering resources, serve as technical liaison with EDA vendors, evaluate and select EDA tools, drive scripting infrastructure, partner with RTL/DFT/Architecture teams, collaborate with foundries
Seniority
Director, strategic leadership & team management
