Design Verification Engineer for DFT
Core
Lead and drive Design for Test (DFT) verification activities for advanced silicon chips, specifically Cisco Silicon One, focusing on validating testability features in AI infrastructure.
Role type
Senior IC Design Verification Engineer (DFT)
Builds
Production silicon chips with embedded test features (scan, MBIST, JTAG, DFT controllers)
Domain
Semiconductor / Hardware Design / AI Infrastructure
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, verification planning, coverage modeling, assertions, RTL debugging, SoC verification
Preferred skills
DFT methodologies (scan insertion, MBIST, ATPG, boundary scan), networking silicon verification, high-performance AI silicon verification, building verification methodologies from scratch
Technologies
SystemVerilog, UVM, JTAG, MBIST, ATPG
Responsibilities
Develop verification plans, environments, checkers, and coverage models for DFT features; Verify DFT architecture and implementation; Debug complex pre-silicon issues across RTL and DFT logic; Contribute to scalable verification methodologies and reusable components.
Seniority
Senior, hands-on IC
