ASIC Engineering Technical Leader- STA
Required skills
Bachelor’s with 10 years of related experience, or Master’s with 5 years of related experience, or PhD with 2 years of related experience. Prior experience with Integration for STA including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. Prior experience in developing timing constraints and signing off timing on blocks/sub system in advanced process nodes. Prior experience with timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery. Prior experience with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.
Preferred skills
Synthesis Tools: Synopsys. DC/DCG/FC. Formal Verification : Synopsys, Formality and Cadence LEC. Parasitic Extraction : Synopsys, Star-RCXT, Cadence Quantus. Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus. Scripting: TCL, Perl is required; Python is a plus.
Technologies
Synopsys, Cadence, TCL, Perl, Python.
Responsibilities
Oversees the definition, architecture and design of high performance ASICs. Oversees all applications and code including methodology of reusable code. Oversees code creation and determines methodology behind coding. Consults for architecture and design decisions for complex areas. Drives design solutions across the business. Creates guidelines and standards. Creates innovative verification strategies. Oversees system level verification using test benches. Ensures culture of code reviews and postmortems. Architects and designs analog/mixed-signal circuits. Reviews complex IC designs and makes recommendations for improvements. Directs the mixed-signal team to define requirements, influences packaging and hardware team to ensure specifications are met. Oversees all physical design functions bringing technical expertise to highly complex scenarios. Interfaces with vendors and design leads on complex issues. Drives different technology design rules to develop innovative packages.
Seniority
Technical Leader.
Domain
ASIC design, STA, silicon architecture, Cisco platforms.
