ASIC STA Engineer
Core
Develop static timing analysis (STA) methodologies, guidelines, and checklists to streamline STA work and resolve design/flow issues for high-speed optical interconnect ASICs.
Role type
ASIC Design Engineer (Static Timing Analysis)
Builds
High-speed optical interconnect products (DSP ASICs, silicon photonic PICs, coherent modules)
Domain
Semiconductor / Optical Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, SystemVerilog, Static Timing Analysis (STA), ASIC Design, Physical Design flow, Spice simulation, PNR correlation
Preferred skills
Prior STA experience
Technologies
Verilog, SystemVerilog, Spice, PNR tools
Responsibilities
Develop methodologies, guidelines, and checklists to streamline STA work; Resolve design and flow issues; Drive execution to ensure progress and accuracy
Seniority
Mid-Senior, hands-on IC
