Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs
Core
Design and develop System-on-Chips (SOCs) that power AI workloads in datacenters by automating design flows and building large-scale solutions to accelerate silicon development.
Role type
Senior ASIC Design Infrastructure & Methodologies Engineer
Builds
Automated design flows, infrastructure, and large-scale solutions for silicon development
Domain
Semiconductor / AI Hardware / ASIC Design
Deliverable
infrastructure
Required skills
ASIC implementation, synthesis, STA, physical design, digital design in communication systems, full-custom analog or RF layout, wireless communications systems, creating and maintaining automation frameworks for Post-Silicon Flow, verification in communication systems, UVM, C, System C, scripting
Preferred skills
RTL coding and debug, performance/power/area analysis and trade-offs, modern ASIC/FPGA design and verification tools, SOC bring-up and post-silicon validation
Technologies
UVM, C, System C
Responsibilities
Develop and implement new methodologies and infrastructure to empower design teams; Enhance and build design flows to boost overall productivity; Collaborate with vendors to evaluate and qualify new design tools and updated tool versions
