ASIC Engineering Technical Lead - DFT
Core
Leading development of Design-for-Test (DFT) solutions for next-generation ASICs used in multi-100G to 1.6T coherent optical communications products.
Role type
Senior IC ASIC Engineering Technical Lead (DFT)
Builds
DFT architectures and test flows for high-speed optical interconnect ASICs
Domain
Semiconductor / Optical Communications / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture implementation, scan insertion, compression/decompression logic, memory/logic BIST, ATPG test pattern generation, RTL debugging, gate-level simulation, Python/Tcl/C++ scripting
Preferred skills
Tapeout execution leadership, ATE tester experience, clock domain crossing analysis, advanced silicon process nodes, Verilog/System Verilog integration
Technologies
Siemens Tessent, Synopsys, Python, Tcl, C++, Verilog, System Verilog, RTL, Gate netlist
Responsibilities
Lead implementation of hierarchical test flow DFT architectures; Generate and deliver ATPG test patterns and drive scan-based diagnosis; Evaluate design readiness for scan insertion via DRC tools; Integrate and verify DFT fabrics and IP within subsystems; Perform simulation runs and debug for non-timing and back annotated timing gate level simulations; Develop test scripts and automate processes
Seniority
Senior, hands-on IC
